ΜΑΡΙΑ ΜΙΧΑΗΛ
ΜΙΧΑΗΛ ΜΑΡΙΑ
MICHAEL MARIA
...
ASSOCIATE PROFESSOR
Department of Electrical and Computer Engineering
Green Park
75, Kallipoleos Ave.
411
22892277
22892260
www.kios.ucy.ac.cy/mmichael

Προσωπικό Προφίλ

Maria K. Michael is an Associate Professor at the Electrical and Computer Engineering Department (ECE), at the University of Cyprus. She holds a BSc and MSc in Computer Science, and a Ph.D. in Engineering Sciences (specialization in Computer Engineering) from Southern Illinois University, USA. Prior to joining the University of Cyprus, she taught as a Lecturer at the ECE Department at Southern Illinois University, and as an Assistant Professor of Computer Science and Engineering at the University of Notre Dame, USA. Maria is also a co-founding academic member of the KIOS Center at the University of Cyprus since 2008. In 2016, she was part of the team that received the very prestigious H2020 TEAMING funding to elevate the KIOS Center to the KIOS Research and Innovation Center of Excellence (KIOS CoE). She currently serves as the Director of Education and Training of the KIOS CoE. She is also the academic coordinator of the newly established MSc program in Intelligent Critical Infrastructure Systems, an innovative and internationally unique MSc program in the topic of monitoring, control and security of critical infrastructure systems (such as electric power systems and intelligent transportation systems), using ICT technologies focusing on intelligent methods and smart IoT-based cyber-physical systems. The program is a collaboration between the ECE Department and KIOS CoE at UCY, and Imperial College London, UK.

At the University of Cyprus, she leads research activities in the areas of dependability and security in embedded and IoT-enabled cyber-physical systems. She has extensive expertise in the areas of electronic design automation (CAD), test, diagnosis, reliability, fault tolerance and safety of large-scale integrated circuits and (safety-critical) embedded systems. Her current research focuses on hardware-enabled security and cyber-security in intelligent embedded systems and cyber-physical systems, optimization of performance and dependability of AI/ML edge intelligence, reliability and security of resource-constrained edge-based accelerators, with applications in intelligent critical infrastructure systems such as smart grids, UAVs, robotics and autonomous vehicles. She has more than 85 publications in refereed journals, book chapters, international conferences and other technical venues. She currently leads a team of fifteen researchers (post-doctoral, PhD, MSc/BSc level).

Her research has been funded by several local and international agencies and industry in Europe and the United States, such as EU FP7, EU H2020, EU COST, NSF, Intel Corp., and the Cyprus Research and Innovation Foundation. She has extensive experience in participating and managing research projects. She has participated in more than 25 funded research programs/grants, 7 with the role of project PI/co-PI and 6 with the role of PI/Co-PI for the UCY/KIOS participation. She currently leads the UCY/KIOS team (PI) in the H2020 SESAME project (Secure and Safe Multi-Robot Systems), focusing on dependability and security in collaborative UAVs for critical infrastructure inspection and emergency response. She is also leading tasks for vulnerability analysis and mitigation techniques from cyber-security threats in the H2020 ELECTRON project (Resilient and Self-healed Electrical Power Nanogrid).

Maria has served as Associate Editor in special issues of the IEEE Transactions in Emerging Topics in Computing and of the ACM Journal on Emerging Technologies in Computing Systems. She is a member of the IEEE, and also a reviewer for multiple conferences and journals. She has been serving regularly on the Steering, Organizing and Program Committees of numerous IEEE and ACM conferences, such as DATE, VTS, ETS, DFTS, VLSISoC, IOLTS, COINS, etc. She was Technical Program Chair for the 28th DFTS’15, Technical Program Chair for the ISVLSI’22, upcoming Technical Program Chair for 29th IEEE ETS’24, General Chair of the 29th DFTS’16, and General Chair for the 22nd ETS’17, as well as technical track/topic/tutorials/special sessions chair for, DATE, VTS, ETS, IOLTS, COINS, etc. She was the elected Steering Committee Vice-Chair of ETS for 2019-2022.

  • Dependability and security in embedded and IoT-based cyber-physical systems
  • Test, diagnosis, reliability, fault-tolerance and safety of integrated circuits and (safety-critical) embedded systems
  • Optimization of performance and dependability/security of AI/ML edge intelligence
  • Reliability and security of resource-constrained edge-based ML/Accelerators
  • Hardware-enabled security in embedded systems
  • Cyber-security in intelligent (ML-based/model-based) cyber-physical systems
  • ML-based fault diagnosis and anomaly classification
  • Graph theory and (parallel) algorithms for automation tools; decision diagrams and SAT

M. Skitsas, C. Nicopoulos and M. K. Michael, “DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors”, IEEE Transactions on Computers, to appear, published online (IEEE Xplore),DOI Bookmark: 10.1109/TC.2015.2449840, June 2015, pp. 1-14.

M. Maniatakos, M. K. Michael and Y. Makris, “Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving”, IEEE Transactions on Very Large Scale Integration, to appear, published online (IEEE Xplore), DOI Bookmark: 10.1109/TVLSI.2014.2365032, November 2014, pp. 1-13.

H. Kim, S. B. Boga, A. Vitkovskiy, S. Hadjitheophanous, P. V. Gratz, V. Soteriou and M. K. Michael, “Use it or Lose it: Proactive, Deterministic Longevity in Future Chip Multiprocessors, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, September 2015, pp. 1-26.

M. Maniatakos, M. K. Michael, C. Tirumurti and Y. Makris, "Revisiting Vulnerability Analysis in Modern Microprocessors", IEEE Transactions on Computers, Vol. 64, No. 9, September 2015, pp. 2664-2674.

M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M. K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, S. Hamdioui, “Dependable Multicore Architectures at Nanoscale: the view from Europe”, IEEE Design & Test, Vol. 32, No. 2, April 2015, pp. 17-28.

 

S. Neophytou and M. K. Michael, “Multiple detection test generation with diversified fault partitioning paths”, Microprocessors and Microsystems - Embedded Hardware Design (MICPRO), Vol. 38, No. 6, August 2014, pp. 585-597.

 

S. Neophytou, C. Christou, and M. K. Michael, “A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.28, No. 6, October 2012, pp. 843-856.

 

C. Ttofis, T. Theocharides, and M. K. Michael, “FPGA-based Laboratory Assignments for NoC-based Manycore Systems”, IEEE Transactions on Education, Vol. 55, No. 2, May 2012, pp. 180-189.

 

S. Neophytou and M. K. Michael, “Test Pattern Generation for Relaxed n-detect Test Sets”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 20, No. 3, March 2012, pp. 410-423.

 

R. Adapa, S. Tragoudas, and M. K. Michael, “Improved Diagnosis Using Enhanced Fault Dominance Relations", Integration, the VLSI Journal, Vol. 44, No. 3, June 2011, pp. 217-228.

 

C. Tofis, A. Papadopoulos, T. Theocharides, M. K. Michael, and D. Doumenis, "An MPSoC-based QAM Modulation Architecture with Run-Time Load-Balancing", EURASIP Journal of Embedded Systems, Vol. 2011 (2011), Article ID 790265, 15 pages.

 

T. Theocharides, M. K. Michael, M. Polycarpou, and A. Dingankar, “Hardware-Enabled Dynamic Resource Allocation for Manycore Systems using Bidding-based System Feedback”, EURASIP Journal on Embedded Systems, Vol. 2010 (2010), Article ID 261434, 21 pages.

 

S. Neophytou and M. K. Michael, “Test Set Generation With a Large Number of Unspecified Bits Using Static and Dynamic TechniquesIEEE Transactions on Computer, Vol. 59, No. 3, March 2010, pp. 301-316.

 

K. Christou, M. K. Michael and S. Tragoudas, “On the use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.24, No. 1 – 3, June 2008, pp. 203-222.

S. Neophytou, M. K. Michael, and S. Tragoudas, “Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 25, No. 12, December 2006, pp. 3026-2035.

M. K. Michael and S. Tragoudas, “Function-based Compact Test Pattern Generation for Path Delay Faults”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 13, No. 8, August 2005, pp. 996-1001.

M. K. Michael, T. Haniotakis, and S. Tragoudas, “A Unified Framework for Generating Propagation Functions for Logic Errors and Events", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 23, No. 6, June 2004, pp. 980-986.

S. Padmanaban, M. K. Michael, and S. Tragoudas, “Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations”, IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003, pp. 305-316.

M. K. Michael and S. Tragoudas, “ATPG Tools for Delay Faults at the Functional level”, ACM Transactions On Design Automation of Electronic Systems (TODAES), Vol. 7, Issue 1, January 2002, pp. 33-57.

Profile Information

Maria K. Michael is an Associate Professor at the Electrical and Computer Engineering Department (ECE), at the University of Cyprus. She holds a BSc and MSc in Computer Science, and a Ph.D. in Engineering Sciences (specialization in Computer Engineering) from Southern Illinois University, USA. Prior to joining the University of Cyprus, she taught as a Lecturer at the ECE Department at Southern Illinois University, and as an Assistant Professor of Computer Science and Engineering at the University of Notre Dame, USA. Maria is also a co-founding academic member of the KIOS Center at the University of Cyprus since 2008. In 2016, she was part of the team that received the very prestigious H2020 TEAMING funding to elevate the KIOS Center to the KIOS Research and Innovation Center of Excellence (KIOS CoE). She currently serves as the Director of Education and Training of the KIOS CoE. She is also the academic coordinator of the newly established MSc program in Intelligent Critical Infrastructure Systems, an innovative and internationally unique MSc program in the topic of monitoring, control and security of critical infrastructure systems (such as electric power systems and intelligent transportation systems), using ICT technologies focusing on intelligent methods and smart IoT-based cyber-physical systems. The program is a collaboration between the ECE Department and KIOS CoE at UCY, and Imperial College London, UK.

At the University of Cyprus, she leads research activities in the areas of dependability and security in embedded and IoT-enabled cyber-physical systems. She has extensive expertise in the areas of electronic design automation (CAD), test, diagnosis, reliability, fault tolerance and safety of large-scale integrated circuits and (safety-critical) embedded systems. Her current research focuses on hardware-enabled security and cyber-security in intelligent embedded systems and cyber-physical systems, optimization of performance and dependability of AI/ML edge intelligence, reliability and security of resource-constrained edge-based accelerators, with applications in intelligent critical infrastructure systems such as smart grids, UAVs, robotics and autonomous vehicles. She has more than 85 publications in refereed journals, book chapters, international conferences and other technical venues. She currently leads a team of fifteen researchers (post-doctoral, PhD, MSc/BSc level).

Her research has been funded by several local and international agencies and industry in Europe and the United States, such as EU FP7, EU H2020, EU COST, NSF, Intel Corp., and the Cyprus Research and Innovation Foundation. She has extensive experience in participating and managing research projects. She has participated in more than 25 funded research programs/grants, 7 with the role of project PI/co-PI and 6 with the role of PI/Co-PI for the UCY/KIOS participation. She currently leads the UCY/KIOS team (PI) in the H2020 SESAME project (Secure and Safe Multi-Robot Systems), focusing on dependability and security in collaborative UAVs for critical infrastructure inspection and emergency response. She is also leading tasks for vulnerability analysis and mitigation techniques from cyber-security threats in the H2020 ELECTRON project (Resilient and Self-healed Electrical Power Nanogrid).

Maria has served as Associate Editor in special issues of the IEEE Transactions in Emerging Topics in Computing and of the ACM Journal on Emerging Technologies in Computing Systems. She is a member of the IEEE, and also a reviewer for multiple conferences and journals. She has been serving regularly on the Steering, Organizing and Program Committees of numerous IEEE and ACM conferences, such as DATE, VTS, ETS, DFTS, VLSISoC, IOLTS, COINS, etc. She was Technical Program Chair for the 28th DFTS’15, Technical Program Chair for the ISVLSI’22, upcoming Technical Program Chair for 29th IEEE ETS’24, General Chair of the 29th DFTS’16, and General Chair for the 22nd ETS’17, as well as technical track/topic/tutorials/special sessions chair for, DATE, VTS, ETS, IOLTS, COINS, etc. She was the elected Steering Committee Vice-Chair of ETS for 2019-2022.

  • Dependability and security in embedded and IoT-based cyber-physical systems
  • Test, diagnosis, reliability, fault-tolerance and safety of integrated circuits and (safety-critical) embedded systems
  • Optimization of performance and dependability/security of AI/ML edge intelligence
  • Reliability and security of resource-constrained edge-based ML/Accelerators
  • Hardware-enabled security in embedded systems
  • Cyber-security in intelligent (ML-based/model-based) cyber-physical systems
  • ML-based fault diagnosis and anomaly classification
  • Graph theory and (parallel) algorithms for automation tools; decision diagrams and SAT

M. Skitsas, C. Nicopoulos and M. K. Michael, “DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors”, IEEE Transactions on Computers, to appear, published online (IEEE Xplore),DOI Bookmark: 10.1109/TC.2015.2449840, June 2015, pp. 1-14.

M. Maniatakos, M. K. Michael and Y. Makris, “Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving”, IEEE Transactions on Very Large Scale Integration, to appear, published online (IEEE Xplore), DOI Bookmark: 10.1109/TVLSI.2014.2365032, November 2014, pp. 1-13.

H. Kim, S. B. Boga, A. Vitkovskiy, S. Hadjitheophanous, P. V. Gratz, V. Soteriou and M. K. Michael, “Use it or Lose it: Proactive, Deterministic Longevity in Future Chip Multiprocessors, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, September 2015, pp. 1-26.

M. Maniatakos, M. K. Michael, C. Tirumurti and Y. Makris, "Revisiting Vulnerability Analysis in Modern Microprocessors", IEEE Transactions on Computers, Vol. 64, No. 9, September 2015, pp. 2664-2674.

M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M. K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, S. Hamdioui, “Dependable Multicore Architectures at Nanoscale: the view from Europe”, IEEE Design & Test, Vol. 32, No. 2, April 2015, pp. 17-28.

 

S. Neophytou and M. K. Michael, “Multiple detection test generation with diversified fault partitioning paths”, Microprocessors and Microsystems - Embedded Hardware Design (MICPRO), Vol. 38, No. 6, August 2014, pp. 585-597.

 

S. Neophytou, C. Christou, and M. K. Michael, “A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.28, No. 6, October 2012, pp. 843-856.

 

C. Ttofis, T. Theocharides, and M. K. Michael, “FPGA-based Laboratory Assignments for NoC-based Manycore Systems”, IEEE Transactions on Education, Vol. 55, No. 2, May 2012, pp. 180-189.

 

S. Neophytou and M. K. Michael, “Test Pattern Generation for Relaxed n-detect Test Sets”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 20, No. 3, March 2012, pp. 410-423.

 

R. Adapa, S. Tragoudas, and M. K. Michael, “Improved Diagnosis Using Enhanced Fault Dominance Relations", Integration, the VLSI Journal, Vol. 44, No. 3, June 2011, pp. 217-228.

 

C. Tofis, A. Papadopoulos, T. Theocharides, M. K. Michael, and D. Doumenis, "An MPSoC-based QAM Modulation Architecture with Run-Time Load-Balancing", EURASIP Journal of Embedded Systems, Vol. 2011 (2011), Article ID 790265, 15 pages.

 

T. Theocharides, M. K. Michael, M. Polycarpou, and A. Dingankar, “Hardware-Enabled Dynamic Resource Allocation for Manycore Systems using Bidding-based System Feedback”, EURASIP Journal on Embedded Systems, Vol. 2010 (2010), Article ID 261434, 21 pages.

 

S. Neophytou and M. K. Michael, “Test Set Generation With a Large Number of Unspecified Bits Using Static and Dynamic TechniquesIEEE Transactions on Computer, Vol. 59, No. 3, March 2010, pp. 301-316.

 

K. Christou, M. K. Michael and S. Tragoudas, “On the use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.24, No. 1 – 3, June 2008, pp. 203-222.

S. Neophytou, M. K. Michael, and S. Tragoudas, “Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 25, No. 12, December 2006, pp. 3026-2035.

M. K. Michael and S. Tragoudas, “Function-based Compact Test Pattern Generation for Path Delay Faults”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 13, No. 8, August 2005, pp. 996-1001.

M. K. Michael, T. Haniotakis, and S. Tragoudas, “A Unified Framework for Generating Propagation Functions for Logic Errors and Events", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 23, No. 6, June 2004, pp. 980-986.

S. Padmanaban, M. K. Michael, and S. Tragoudas, “Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations”, IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003, pp. 305-316.

M. K. Michael and S. Tragoudas, “ATPG Tools for Delay Faults at the Functional level”, ACM Transactions On Design Automation of Electronic Systems (TODAES), Vol. 7, Issue 1, January 2002, pp. 33-57.